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1 v id0 pwrgd v id1 v id4 v id3 v id4 v id3 v id2 comp 12v 5v 1.2 h gate(h) gate(l) pgnd 1200 f/10v x 3 1 f ss lgnd 330pf 0.1 f v id0 1200 f 10v x 5 v id2 v id1 pentium ii system CS5166 v fb c off v cc pwrgd i sense 3.0m ? 1000pf 510 3.3k 0.1 f 0.1 f features v 2 tm control topology dual n-channel design 125ns controller transient response excess of 1mhz operation 5-bit dac with 1% tolerance power-good output with internal delay adjustable hiccup mode over current protection complete pentium ? ii system requires just 21 components 5v and 12v operation adaptive voltage positioning remote sense capability current sharing capability v cc monitor overvoltage protection (ovp) programmable soft start 200ns pwm blanking 65ns fet non-overlap 40ns gate rise and fall times (3.3nf load) package options CS5166 5-bit synchronous cpu controller with power-good and current limit CS5166 description the CS5166 is a synchronous dual nfet buck regulator controller. it is designed to pow- er the core logic of the latest high performance cpus. it uses the v 2 tm control method to achieve the fastest possible transient response and best overall regula- tion. it incorporates many addi- tional features required to ensure the proper operation and protec- tion of the cpu and power sys- tem. the CS5166 provides the industry?s most highly integrat- ed solution, minimizing external component count, total solution size, and cost. the CS5166 is specifically designed to power intel?s pentium ? ii processor and includes the following features: 5-bit dac with 1% tolerance, power-good output, adjustable hiccup mode over-current pro- tection, v cc monitor, soft start, adaptive voltage positioning, over-voltage protection, remote sense and current sharing capa- bility. the CS5166 will operate over a 4.15 to 14v range and is available in a 16 lead wide body surface mount package. application diagram 1 16 lead so wide a company ? v id0 v id1 v id2 v id3 i sense c off ss v id4 v fb comp lgnd pwrgd gate(l) pgnd gate(h) v cc pentium is a registered trademark of intel corporation. 5v to 2.8v @ 14.2a for 300mhz pentium? ii v 2 is a trademark of switch power, inc. rev. 6/28/99 cherry semiconductor corporation 2000 south county trail, east greenwich, ri 02818 tel: (401)885-3600 fax: (401)885-5786 email: info@cherry-semi.com web site: www.cherry-semi.com
absolute maximum ratings pin symbol pin name v max v min i source i sink 2 package pin # pin symbol function package pin description CS5166 v cc ic power input 16v -0.3v n/a 1.5a peak 200ma dc ss soft start capacitor 6v -0.3v 200a 10a comp compensation capacitor 6v -0.3v 10ma 1ma v fb voltage feedback and current 6v -0.3v 1ma 1ma sense comparator input c off off-time capacitor 6v -0.3v 1ma 50ma v id0-4 voltage id dac inputs 6v -0.3v 1ma 10a gate(h) high-side fet driver 16v -0.3v 1.5a peak 1.5a peak 200ma dc 200ma dc gate(l) low-side fet driver 16v -0.3v 1.5a peak 1.5a peak 200ma dc 200ma dc i sense current sense comparator input 6v -0.3v 1ma 1ma pwrgd power-good output 6v -0.3v 10a 30ma pgnd power ground 0v 0v 1.5a peak n/a 200ma dc lgnd logic ground 0v 0v 100ma n/a 1,2,3,4,6 v ido ? v id4 voltage id dac inputs. these pins are internally pulled up to 5v if left open. v id4 selects the dac range. when v id4 is high (logic one), the error amp reference range is 2.125v to 3.525v with 100mv increments. when v id4 is low (logic zero), the error amp reference voltage is 1.325v to 2.075v with 50mv increments. 5 ss soft start pin. a capacitor from this pin to lgnd sets the soft start and fault timing. 7c off off-time capacitor pin. a capacitor from this pin to lgnd sets both the normal and extended off time. 8i sense current sense comparator inverting input 9v cc input power supply pin. 10 gate(h) high side switch fet driver pin. 11 pgnd high current ground for the gate(h) and gate(l) pins. 12 gate(l) low side synchronous fet driver pin. 13 pwrgd power-good output. open collector output drives low when v fb is out of regulation. 14 lgnd reference ground. all control circuits are referenced to this pin. 15 comp error amp output. pwm comparator reference input. a capacitor to lgnd provides error amp compensation. 16 v fb error amp, pwm comparator feedback input, current sense comparator non-inverting input, and pwrgd comparator input. operating junction temperature, t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 150c lead temperature soldering: reflow (smd styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sec max. above 183 ? c, 230 ? c peak storage temperature range, t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 to 150 ? c
CS5166 3 electrical characteristics: 0 ? c < t a < 70 ? c; 0 ? c < t j < 125 ? c; 8v < v cc < 14v; 2.0v dac code (v id4 = v id3 = v id2 = v id1 =0, v id0 = 1), c gate(h ) = c gate(l) = 3.3nf, c off = 330pf, c ss = 0.1f; unless otherwise stated. parameter test conditions min typ max unit v cc supply current operating 1v 2.5v 180 400 800 a open loop gain note 1 50 60 db unity gain bandwidth note 1 0.5 2 mhz psrr @ 1khz note 1 60 85 db gate(h) and gate(l) high voltage at 100ma measure v cc ?gate 1.2 2.0 v low voltage at 100ma measure gate 1.0 1.5 v rise time 1.6v < gate < (v cc ? 2.5v) 40 80 ns fall time (v cc ? 2.5v) >gate > 1.6v 40 80 ns gate(h) to gate(l) delay gate(h)<2v, gate(l)>2v 30 65 100 ns gate(l) to gate(h) delay gate(l)<2v, gate(h)>2v 30 65 100 ns gate pull-down resistance to pgnd (note 1) 20 50 115 k ? over current detection current limit voltage v fb = 0v to 3.5v 55 76 130 mv 8v < v cc < 12v + 10% i sense bias current i sense = 2.8v 13 30 50 a fault protection ss charge time v fb = 3v, v isense = 2.8v 1.6 3.3 5.0 ms ss pulse period v fb = 3v, v isense = 2.8v 25 100 200 ms ss duty cycle (charge time/period) 100 1.0 3.3 6.0 %
CS5166 4 electrical characteristics: 0 ? c < t a < 70 ? c; 0 ? c < t j < 125 ? c; 8v < v cc < 14v; 2.0v dac code (v id4 = v id3 = v id2 = v id1 =0, v id0 = 1), c gate(h ) = c gate(l) = 3.3nf, c off = 330pf, c ss = 0.1f; unless otherwise stated. parameter test conditions min typ max unit fault protection continued ss comp clamp voltage v fb = 2.7v, v ss = 0v 0.50 0.95 1.10 v v fb low comparator increase v fb till normal off-time 0.9 1.0 1.1 v pwm comparator transient response v fb = 1.2v to 5v 500ns after gate(h) 115 175 ns (after blanking time) to gate(h) = (v cc ? 1v) to 1v minimum pulse width drive v fb 1.2v to 5v upon gate(h) 100 200 300 ns (blanking time) rising edge (> v cc ? 1v), measure gate(h) pulse width c off normal off-time v fb = 2.7v 1.0 1.6 2.3 s extended off-time v ss = v fb = 0v 5.0 8.0 12.0 s time-out timer time-out time v fb = 2.7v, measure gate(h) 10 30 50 s pulse width fault duty cycle v fb = 0v 30 50 70 % voltage identification dac accuracy (all codes except 11111) measure v fb = comp, (c off = gnd) -1.0 1.0 % v id4 v id3 v id2 v id1 v id0 25 ? c t j 125 ? c, v cc = 12v 1 0 0 0 0 3.489 3.525 3.560 v 1 0 0 0 1 3.390 3.425 3.459 v 1 0 0 1 0 3.291 3.325 3.358 v 1 0 0 1 1 3.192 3.225 3.257 v 1 0 1 0 0 3.093 3.125 3.156 v 1 0 1 0 1 2.994 3.025 3.055 v 1 0 1 1 0 2.895 2.925 2.954 v 1 0 1 1 1 2.796 2.825 2.853 v 1 1 0 0 0 2.697 2.725 2.752 v 1 1 0 0 1 2.598 2.625 2.651 v 1 1 0 1 0 2.499 2.525 2.550 v 1 1 0 1 1 2.400 2.425 2.449 v 1 1 1 0 0 2.301 2.325 2.348 v 1 1 1 0 1 2.202 2.225 2.247 v 1 1 1 1 0 2.103 2.125 2.146 v 0 0 0 0 0 2.054 2.075 2.095 v 0 0 0 0 1 2.004 2.025 2.045 v 0 0 0 1 0 1.955 1.975 1.994 v 0 0 0 1 1 1.905 1.925 1.944 v
CS5166 5 parameter test conditions min typ max unit threshold accuracy lower threshold upper threshold min typ max min typ max units % of nominal v id code -12 -8.5 -5 5 8.5 12 % dac code v id4 v id3 v id2 v id1 v id0 1 0 0 0 0 3.102 3.225 3.348 3.701 3.824 3.948 v 1 0 0 0 1 3.014 3.133 3.253 3.596 3.716 3.836 v 1 0 0 1 0 2.926 3.042 3.158 3.491 3.607 3.724 v 1 0 0 1 1 2.838 2.950 3.063 3.386 3.499 3.612 v 1 0 1 0 0 2.750 2.859 2.968 3.281 3.390 3.500 v 1 0 1 0 1 2.662 2.767 2.873 3.176 3.282 3.388 v 1 0 1 1 0 2.574 2.676 2.778 3.071 3.173 3.276 v 1 0 1 1 1 2.486 2.584 2.683 2.966 3.065 3.164 v 1 1 0 0 0 2.398 2.493 2.588 2.861 2.956 3.052 v 1 1 0 0 1 2.310 2.401 2.493 2.756 2.848 2.940 v 1 1 0 1 0 2.222 2.310 2.398 2.651 2.739 2.828 v electrical characteristics: 0 ? c < t a < 70 ? c; 0 ? c < t j < 125 ? c; 8v < v cc < 14v; 2.0v dac code (v id4 = v id3 = v id2 = v id1 =0, v id0 = 1), c gate(h ) = c gate(l) = 3.3nf, c off = 330pf, c ss = 0.1f; unless otherwise stated. accuracy (all codes except 11111) measure v fb = comp, (c off = gnd) -1.0 1.0 % v id4 v id3 v id2 v id1 v id0 0 0 1 0 0 1.856 1.875 1.893 v 0 0 1 0 1 1.806 1.825 1.843 v 0 0 1 1 0 1.757 1.775 1.792 v 0 0 1 1 1 1.707 1.725 1.742 v 0 1 0 0 0 1.658 1.675 1.691 v 0 1 0 0 1 1.608 1.625 1.641 v 0 1 0 1 0 1.559 1.575 1.590 v 0 1 0 1 1 1.509 1.525 1.540 v 0 1 1 0 0 1.460 1.475 1.489 v 0 1 1 0 1 1.410 1.425 1.439 v 0 1 1 1 0 1.361 1.375 1.388 v 0 1 1 1 1 1.311 1.325 1.338 v 1 1 1 1 1 1.219 1.247 1.269 v input threshold v id4 , v id3 , v id2 , v id1 , v id0 1.0 1.25 2.4 v input pull-up resistance v id4 , v id3 , v id2 , v id1 , v id0 25 50 100 k ? input pull-up voltage 4.85 5.00 5.15 v power-good output low to high delay v fb = (0.8 v dac ) to v dac 30 65 110 s high to low delay v fb = v dac to (0.8 v dac ) 30 75 120 s output low voltage v fb = 2.4v, i pwrgd = 500a 0.2 0.3 v sink current limit v fb = 2.4v, pwrgd = 1v 0.5 4.0 15.0 ma
threshold accuracy lower threshold upper threshold min typ max min typ max units block diagram q v id1 ss v id0 v cc v gate(h) pgnd v gate(l) v id2 v id3 c off maximum on-time timeout v cc r q s c off one shot ss high comparator fault latch 2.5v error amplifier 30 a v id4 - + - + - + pwm comparator ss low comparator r q s q r q s 2 a 5v 60 a normal off-time extended off-time timeout time out timer edge triggered off-time timeout fault gate(h) = on gate(h) = off pgnd pwm latch 0.7v comp - + lgnd v fb pwrgd 65 s delay - + - + pwm comp blanking - + v cc monitor 5 bit dac -8.5% +8.5% fault i sense comparator 76mv v cc i sense - + v fb low comparator - + 1v 3.87v 3.95v 6 CS5166 electrical characteristics: 0 ? c < t a < 70 ? c; 0 ? c < t j < 125 ? c; 8v < v cc < 14v; 2.0v dac code (v id4 = v id3 = v id2 = v id1 =0, v id0 = 1), c gate(h ) = c gate(l) = 3.3nf, c off = 330pf, c ss = 0.1f; unless otherwise stated. % of nominal v id code -12 -8.5 -5 5 8.5 12 % dac code v id4 v id3 v id2 v id1 v id0 1 1 0 1 1 2.134 2.218 2.303 2.546 2.631 2.716 v 1 1 1 0 0 2.046 2.127 2.208 2.441 2.522 2.604 v 1 1 1 0 1 1.958 2.035 2.113 2.336 2.414 2.492 v 1 1 1 1 0 1.870 1.944 2.018 2.231 2.305 2.380 v 0 0 0 0 0 1.826 1.898 1.971 2.178 2.251 2.324 v 0 0 0 0 1 1.782 1.8520 1.923 2.126 2.197 2.268 v 0 0 0 1 0 1.738 1.807 1.876 2.073 2.142 2.212 v 0 0 0 1 1 1.694 1.761 1.828 2.021 2.088 2.156 v 0 0 1 0 0 1.650 1.715 1.781 1.968 2.034 2.100 v 0 0 1 0 1 1.606 1.669 1.733 1.916 1.980 2.044 v 0 0 1 1 0 1.562 1.624 1.686 1.863 1.925 1.988 v 0 0 1 1 1 1.518 1.578 1.638 1.811 1.871 1.932 v 0 1 0 0 0 1.474 1.532 1.591 1.758 1.817 1.876 v 0 1 0 0 1 1.430 1.486 1.543 1.706 1.763 1.820 v 0 1 0 1 0 1.386 1.441 1.496 1.653 1.708 1.764 v 0 1 0 1 1 1.342 1.395 1.448 1.601 1.654 1.708 v 0 1 1 0 0 1.298 1.349 1.401 1.548 1.600 1.652 v 0 1 1 0 1 1.254 1.303 1.353 1.496 1.546 1.596 v 0 1 1 1 0 1.210 1.258 1.306 1.443 1.491 1.540 v 0 1 1 1 1 1.166 1.212 1.258 1.391 1.437 1.484 v 1 1 1 1 1 1.094 1.138 1.181 1.306 1.349 1.393 v note 1: guaranteed by design, not 100% tested in production
CS5166 7 v 2 tm control method the v 2 tm method of control uses a ramp signal that is gen- erated by the esr of the output capacitors. this ramp is proportional to the ac current through the main inductor and is offset by the value of the dc output voltage. this control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is gen- erated from the output voltage itself. this control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. figure 1: v 2 tm control diagram. the v 2 tm control method is illustrated in figure 1. the out- put voltage is used to generate both the error signal and the ramp signal. since the ramp signal is simply the output voltage, it is affected by any change in the output regard- less of the origin of that change. the ramp signal also con- tains the dc portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. a change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the v 2 tm control scheme to compensate the duty cycle. since the change in inductor current modifies the ramp signal, as in current mode control, the v 2 tm control scheme has the same advantages in line transient response. a change in load current will have an affect on the output voltage, altering the ramp signal. a load step immediately changes the state of the comparator output, which controls the main switch. load transient response is determined only by the comparator response time and the transition speed of the main switch. the reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. the error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this ?slow? feedback loop is to provide dc accuracy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effective- ly filtered. the bode plot in figure 2 shows the gain and phase margin of the CS5166 single pole feedback loop and demonstrates the overall stability of the CS5166-based regulator. figure 2: feedback loop bode plot. line and load regulation are drastically improved because there are two independent voltage loops. a voltage mode controller relies on a change in the error signal to compen- sate for a deviation in either line or load voltage. this change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. a current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. the v 2 tm method of control maintains a fixed error signal for both line and load varia- tion, since the ramp signal is affected by both line and load. constant off-time to maximize transient response, the CS5166 uses a constant off-time method to control the rate of output pulses. during normal operation, the off-time of the high side switch is terminated after a fixed period, set by the c off capacitor. to maintain regulation, the v 2 tm control loop varies switch on-time. the pwm comparator moni- tors the output voltage ramp, and terminates the switch on-time. constant off-time provides a number of advantages. switch duty cycle can be adjusted from 0 to 100% on a pulse-by pulse basis when responding to transient condi- tions. both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. pwm slope compensation to avoid sub-harmonic oscillations at high duty cycles is avoided. switch on-time is limited by an internal 30s (typical) timer, minimizing stress to the power components programmable output the CS5166 is designed to provide two methods for pro- gramming the output voltage of the power supply. a five bit on board digital to analog converter (dac) is used to program the output voltage within two different ranges. .1 f 10k open loop 49.63 bw 62.3 khz phase margin 81.9 reference voltage + c ? e + ? ramp signal v fb error signal gate(h) gate(l) error amplifier comp pwm comparator theory of operation application information
the first range is 2.125v to 3.525v in 100mv steps, the sec- ond is 1.325v to 2.075v in 50mv steps, depending on the digital input code. if all five bits are left open, the CS5166 enters adjust mode. in adjust mode, the designer can choose any output voltage by using resistor divider feed- back to the v fb pin, as in traditional controllers. the CS5166 is specifically designed to meet or exceed intel?s pentium ? ii specifications. start-up until the voltage on the v cc supply pin exceeds the 3.95v monitor threshold, the soft start and gate pins are held low. the fault latch is reset (no fault condition). the out- put of the error amp (comp) is pulled up to 1v by the comp clamp. when the v cc pin exceeds the monitor threshold, the gate(h) output is activated, and the soft start capacitor begins charging. the gate(h) output will remain on, enabling the nfet switch, until terminated by either the pwm comparator, or the maximum on-time timer. if the maximum on-time is exceeded before the regulator output voltage achieves the 1v level, the pulse is terminat- ed. the gate(h) pin drives low, and the gate(l) pin drives high for the duration of the extended off-time. this time is set by the time-out timer and is approximately equal to the maximum on-time, resulting in a 50% duty cycle. the gate(l) pin will then drive low, the gate(h) pin will drive high, and the cycle repeats. when regulator output voltage achieves the 1v level pre- sent at the comp pin, regulation has been achieved and normal off-time will ensue. the pwm comparator termi- nates the switch on-time, with off-time set by the c off capacitor. the v 2 tm control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amp. the soft start and comp capacitors will charge to their final levels, providing a controlled turn-on of the regulator output. regulator turn-on time is determined by the comp capacitor charging to its final value. its voltage is limited by the soft start comp clamp and the voltage on the soft start pin. figure 3: demonstration board startup in response to increasing 12v and 5v input voltages. extended off time is followed by normal off time operation when output voltage achieves regulation to the error amplifier output. figure 4: demonstration board startup waveforms. figure 5: demonstration board enable startup waveforms. normal operation during normal operation, switch off-time is constant and set by the c off capacitor. switch on-time is adjusted by the v 2 tm control loop to maintain regulation. this results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. output voltage ripple will be determined by inductor rip- ple current and the esr of the output capacitors (see figures 6 and 7). trace 1 - regulator output voltage (5v/div.) trace 2 - inductor switching node (5v/div.) trace 1 - regulator output voltage (1v/div.) trace 3 - comp pin (error amplifier output) (1v/div.) trace 4 - soft start pin (2v/div.) trace 1 - regulator output voltage (1v/div.) trace 2 - inductor switching node (2v/div.) trace 3 - 12v input (v cc ) (5v/div.) trace 4 - 5v input (1v/div.) CS5166 8 application information: continued
figure 6: normal operation showing output inductor ripple current and output voltage ripple, 0.5a load, v out = +2.825v (dac = 10111). figure 7: normal operation showing output inductor ripple current and output voltage ripple, i load = 14a, v out = +2.825v (dac = 10111). transient response the CS5166 v 2 tm control loop?s 150ns reaction time pro- vides unprecedented transient response to changes in input voltage or output current. pulse-by-pulse adjustment of duty cycle is provided to quickly ramp the inductor cur- rent to the required level. since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. overall load transient response is further improved through a feature called ?adaptive voltage positioning?. this technique pre-positions the output capacitors voltage to reduce total output voltage excursions during changes in load. holding tolerance to 1% allows the error amplifiers refer- ence voltage to be targeted +25mv high without compro- mising dc accuracy. a ?droop resistor?, implemented through a pc board trace, connects the error amps feed- back pin (v fb ) to the output capacitors and load and car- ries the output current. with no load, there is no dc drop across this resistor, producing an output voltage tracking the error amps, including the +25mv offset. when the full load current is delivered, a 50mv drop is developed across this resistor. this results in output voltage being offset - 25mv low. the result of adaptive voltage positioning is that addition- al margin is provided for a load transient before reaching the output voltage specification limits. when load current suddenly increases from its minimum level, the output capacitor is pre-positioned +25mv. conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre-positioned -25mv (see figures 8, 9, and 10). for best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. if the maximum on-time is exceeded while responding to a sudden increase in load current, a normal off-time occurs to prevent saturation of the output inductor. figure 8: output voltage transient response to a 14a load pulse, v out = 2.825v (dac = 10111). figure 9: output voltage transient response to a 14a load step, v out = 2.825v (dac = 10111). trace 1 - gate(h) (10v/div) trace 2 - inductor switching node (5v/div) trace 3 -load current (5a/div) trace 4 - v out (100mv/div) trace 3 -load current (5a/10mv/div) trace 4 - v out (100mv/div) trace 1 - gate(h) (10/div) trace 2 - inductor switching node (5v/div) trace 3 - output inductor ripple current (2a/div) trace 4 - v out ripple (20mv/div) trace 1 gate (h) (10v/div) trace 2 inductor switching node (5v/div) trace 3 output inductor ripple current (2a/div) trace 4 v out ripple (20mv/div) CS5166 9 application information: continued
figure 10: output voltage transient response to a 14a load turn-off, v out = +2.825v (dac = 10111). power supply sequencing the CS5166 offers inherent protection from undefined start-up conditions, regardless of the 12v and 5v supply power-up sequencing. the turn-on slew rates of the 12v and 5v power supplies can be varied over wide ranges without affecting the output voltage or causing detrimental effects to the buck regulator. over-current protection a loss-less hiccup mode current limit protection feature is provided, requiring only the soft start capacitor to imple- ment. the CS5166 provides overcurrent protection by sens- ing the current through a ?droop? resistor, using an inter- nal current sense comparator. the comparator compares this voltage drop to an internal reference voltage of 76mv (typical). if the voltage drop across the ?droop? resistor exceeds this threshold, the current sense comparator allows the fault latch to be set. this causes the regulator to stop switching. during this over current condition, the CS5166 stays off for the time it takes the soft start capacitor to slowly discharge by a 2a current source until it reaches its lower 0.7v threshold. at that time the regulator attempts to restart normally by delivering short gate pulses to both fets. the CS5166 will operate initially in its extended off time mode with a 50% duty cycle, while the soft start capacitor is charged with a 60a charge current. the gates will switch on while the soft start capacitor is charged to its upper 2.7v threshold. during an overload condition the soft start charge /dis- charge current ratio sets the duty cycle for the pulses (2a/60a = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%) when v fb is less than 1v. the soft start hiccup pulses last for a 3ms period at the end of which the duty cycle repeats if a fault is detected, otherwise normal operation resumes. this protection scheme minimizes thermal stress to the reg- ulator components, input power supply, and pc board traces, as the over current condition persists. upon removal of the overload, the fault latch is cleared, allowing normal operation to resume. the current limit trip point can be adjusted through an external resistor, providing the user with the current limit set-point flexibility. figure 11: demonstration board hiccup mode short circuit protection. gate pulses are delivered while the soft start capacitor charges, and cease during discharge. figure 12: demonstration board start up with regulator output shorted to ground. overvoltage protection overvoltage protection (ovp) is provided as result of the normal operation of the v 2 tm control topology and requires no additional external components. the control loop responds to an overvoltage condition within 100ns, causing the top mosfet to shut off, disconnecting the regulator from its input voltage. the bottom mosfet is then activat- ed, resulting in a ?crowbar? action to clamp the output voltage and prevent damage to the load (see figures 13 and 14). the regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. the bottom fet and board trace must be properly designed to implement the ovp function. if a dedicated ovp output is required, it can be implemented using the circuit in figure 15. in this figure the ovp signal will go high (overvoltage condition), if the output voltage (v core ) exceeds 20% of the voltage set by the particular dac code trace 4 = 5v from pc power supply (2v/div.) trace 2 = inductor switching node (2v/div.) trace 4 - 5v supply voltage (2v/div.) trace 3 - soft start timing capacitor (1v/div.) trace 2 - inductor switching node (2v/div.) protection and monitoring features trace 1 - gate(h) (10v/div) trace 2 - inductor switching node (5v/div) trace 3 -load current (5a/div) trace 4 - v out (100mv/div) CS5166 10 application information: continued
and provided that pwrgd is low. it is also required that the overvoltage condition be present for at least the pwrgd delay time for the ovp signal to be activated. the resistor values shown in figure 15 are for v dac = +2.8v (dac = 10111). the v ovp (overvoltage trip-point) can be set using the following equation: v ovp = v beq3 ( 1 + ) figure 13: ovp response to an input-to-output short circuit by immedi- ately providing 0% duty cycle, crow-barring the input voltage to ground. figure 14: ovp response to an input-to-output short circuit by pulling the input voltage to ground. figure 15: circuit to implement a dedicated ovp output using the CS5166. power-good circuit the power-good pin (pin 13) is an open-collector signal consistent with ttl dc specifications. it is externally pulled -up, and is pulled low (below 0.3v) when the regu- lator output voltage typically exceeds 8.5% of the nomi- nal output voltage. maximum output voltage deviation before power-good is pulled low is 12%. figure 16: pwrgd signal becomes logic high as v out enters -8.5% of lower pwrgd threshold, v out = +2.825v (dac = 10111). figure 17: power-good response to an out of regulation condition. trace 1 pwrgd (2v/div) trace 4 v fb (1v/div) trace 2 - pwrgd (2v/div) trace 4 - v out (1v/div) 2.825v +5v +5v v core CS5166 pwrgd q1 2n3906 2n3904 q2 2n3906 q3 r1 r2 ovp 10k 20k 10k 5k 10k 15k 56k trace 4 = 5v from pc power supply (2v/div.) trace 1 = regulator output voltage (1v/div.) trace 4 = 5v from pc power supply (5v/div.) trace1 = regulator output voltage (1v/div.) trace 2 = inductor switching node (5v/div.) r2 r1 CS5166 11 application information: continued
figure 17 shows the relationship between the regulated output voltage v fb and the power-good signal. to prevent power-good from interrupting the cpu unnecessarily, the CS5166 has a built-in delay to prevent noise at the v fb pin from toggling power-good. the internal time delay is designed to take about 75s for power-good to go low and 65s for it to recover. this allows the power-good signal to be completely insensitive to out of regulation conditions that are present for a duration less than the built in delay (see figure 18). it is therefore required that the output voltage attains an out of regulation or in regulation level for at least the built- in delay time duration before the power-good signal can change state. figure 18: power-good is insensitive to out of regulation conditions that are present for a duration less than the built in delay. external output enable circuit on/off control of the regulator can be implemented through the addition of two additional discrete compo- nents (see figure 19). this circuit operates by pulling the soft start pin high, and the i sense pin low, emulating a cur- rent limit condition. figure 19: implementing shutdown with the CS5166. selecting external components the CS5166 buck regulator can be used with a wide range of external power components to optimize the cost and performance of a particular design. the following informa- tion can be used as general guidelines to assist in their selection. nfet power transistors both logic level and standard fets can be used. the refer- ence designs derive gate drive from the 12v supply which is generally available in most computer systems and utilize logic level fets. a charge pump may be easily implement- ed to support 5v only systems. multiple fet?s may be par- alleled to reduce losses and improve efficiency and thermal management. voltage applied to the fet gates depends on the applica- tion circuit used. both upper and lower gate driver outputs are specified to drive to within 1.5v of ground when in the low state and to within 2v of their respective bias supplies when in the high state. in practice, the fet gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller ic. for the typical appli- cation where v cc = 12v and 5v is used as the source for the regulator output current, the following gate drive is provided: v gs (top) = 12v - 5v = 7v, v gs(bottom) = 12v, (see figure 20). figure 20: gate drive waveforms depicting rail to rail swing. trace 3 = gate(h) (10v/div.) trace 1= gate(h) - 5v in trace 4 = gate(l) (10v/div.) trace 2 = inductor switching node (5v/div.) shutdown input 5v i sense CS5166 ss 5 8 in4148 mmun2111t1 (sot-23) trace 1 pwrgd (2v/div) trace 4 v fb (1v/div) CS5166 12 application information: continued
13 application information: continued CS5166 figure 21: normal operation showing the guaranteed non-overlap time between the high and low - side mosfet gate drives, i load = 14a. the CS5166 provides adaptive control of the external nfet conduction times by guaranteeing a typical 65ns non-over- lap (as seen in figure 21) between the upper and lower mosfet gate drive pulses. this feature eliminates the potentially catastrophic effect of ?shoot-through current?, a condition during which both fets conduct causing them to overheat, self-destruct, and possibly inflict irreversible damage to the processor. the most important aspect of fet performance is rds on , which effects regulator efficiency and fet thermal man- agement requirements. the power dissipated by the mosfets may be estimated as follows: switching mosfet: power = i load 2 rds on duty cycle synchronous mosfet: power = i load 2 rds on (1 - duty cycle) duty cycle = off time capacitor (c off ) the c off timing capacitor sets the regulator off time: t off = c off 4848.5 the preceding equation for duty cycle can also be used to calculate the regulator switching frequency and select the c off timing capacitor: c off = where period = . schottky diode for synchronous fet for synchronous operation, a schottky diode may be placed in parallel with the synchronous fet to conduct the inductor current upon turn off of the switching fet to improve efficiency. the CS5166 reference circuit does not use this device due to its excellent design. instead, the body diode of the synchronous fet is utilized to reduce cost and conducts the inductor current. for a design operating at 200khz or so, the low non-overlap time combined with schottky forward recovery time may make the benefits of this device not worth the additional expense. the power dissipation in the synchronous mosfet due to body diode conduction can be estimated by the following equation: power = v bd i load conduction time switching fre- quency where v bd = the forward drop of the mosfet body diode. for the CS5166 demonstration board: power = 1.6v 14.2a 100ns 200khz = 0.45w this is only 1.1% of the 40w being delivered to the load. ?droop? resistor for adaptive voltage positioning adaptive voltage positioning is used to help keep the out- put voltage within specification during load transients. to implement adaptive voltage positioning a ?droop resistor? must be connected between the output inductor and output capacitors and load. this resistor carries the full load current and should be chosen so that both dc and ac tolerance limits are met. an embedded pc trace resistor has the distinct advantage of near zero cost implementa- tion. however, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation causes the thick- ness of the pcb layer to vary. 2) the mismatch of l/w, and 3) temperature variation. 1) sheet resistivity for one ounce copper, the thickness variation is typically 1.15 mil to 1.35 mil. therefore the error due to sheet resistivity is: = 16% 2) mismatch due to l/w the variation in l/w is governed by variations due to the pcb manufacturing process that affect the geometry and the power dissipation capability of the droop resistor. the error due to l/w mismatch is typically 1% 1.35 - 1.15 1.25 1 switching frequency period (1-duty cycle) 4848.5 v out + (i load rds on of synch fet ) v in + (i load rds on of synch fet ) - (i load rds on of switch fet ) trace 1 - gate(h) (5v/div) trace 2 - gate(l) (5v/div)
CS5166 14 3) thermal considerations due to i 2 r power losses the surface temperature of the droop resistor will increase causing the resistance to increase. also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula: r = r 20 [1+ 20 ( ? 20)] where: r 20 = resistance at 20 ? c = t = operating temperature r = desired droop resistor value for temperature t = 50 ? c, the % r change = 12% droop resistor tolerance tolerance due to sheet resistivity variation 16% tolerance due to l/w error 1% tolerance due to temperature variation 12% total tolerance for droop resistor 29% in order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. this voltage drop has to be such that the output voltage full load is above the minimum dc tolerance spec. v droop(typ) = example: for a 300mhz pentium ? ii, the dc accuracy spec is 2.74 < v cc(core) < 2.9v, and the ac accuracy spec is 2.67v < v cc(core) <2.93v. the CS5166 dac output volt- age is +2.796v < v dac < +2.853v. in order not to exceed the dc accuracy spec, the voltage drop developed across the resistor must be calculated as follows: v droop(typ) = = = 43mv with the CS5166 dac accuracy being 1%, the internal error amplifier?s reference voltage is trimmed so that the output voltage will be 25mv high at no load. with no load, there is no dc drop across the resistor, producing an out- put voltage tracking the error amplifier output voltage, including the offset. when the full load current is deliv- ered, a drop of -43mv is developed across the resistor. therefore, the regulator output is pre-positioned at 25mv above the nominal output voltage before a load turn-on. the total voltage drop due to a load step is ? v-25mv and the deviation from the nominal output voltage is 25mv smaller than it would be if there was no droop resistor. similarly at full load the regulator output is pre-positioned at 18mv below the nominal voltage before a load turn-off. the total voltage increase due to a load turn-off is ? v-18mv and the deviation from the nominal output voltage is 18mv smaller than it would be if there was no droop resis- tor. this is because the output capacitors are pre-charged to value that is either 25mv above the nominal output voltage before a load turn-on or, 18mv below the nominal output voltage before a load turn-off (see figure 8). obviously, the larger the voltage drop across the droop resistor (the larger the resistance), the worse the dc and load regulation, but the better the ac transient response. current limit setpoint calculations the following is the design equation used to set the cur- rent limit trip point by determining the value of the embedded pcb trace used as a current sensing element. the current limit setpoint has to be higher than the normal full load current. attention has to be paid to the current 2.796v-2.74v 1.3 [v dac(min) -v dc pentium?ii(min) ] 1+r droop(tolerance) [v dac(min) -v dc(min) ] 1+r droop(tolerance) 0.00393 ? c application information: continued v in v out v fb i sense ifb isense q1 q2 lr droop rfb r isense + - v th current limit comparator CS5166 c out i sense figure 22: circuit used to determine the voltage across the droop resistor that will trip the internal current sense comparato r.
15 rating of the external power components as these are the first to fail during an overload condition. the mosfet continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the cur- rent limit trip point. for example the irl 3103s (d 2 pak) mosfet has a continuous drain current rating of 45a at v gs = 10v and t c = 100 ? c. temperature curves on mos- fet manufacturers? data sheets allow the designer to determine the mosfet drain current at a particular v gs and t j (junction temperature). this, in turn, will assist the designer to set a proper current limit, without causing device breakdown during an overload condition. for a 300mhz pentium ? ii cpu the full load is 14.2a. the internal current sense comparator current limit voltage limits are: 55mv < v th < 130mv. also, there is a 29% total variation in r sense as discussed in the previous section. we select the value of the current sensing element (embed- ded pcb trace) for the minimum current limit setpoint: r sense(max) = ? r sense 1.29 = ? r sense 1.29 = 3.87m ? ? r sense = 3m ? we calculate the range of load currents that will cause the internal current sense comparator to detect an overload condition. from the overcurrent detection data section (pg 3), nominal current limit setpoint v th(typ) = 76mv. i cl(nom) = maximum current limit setpoint therefore , i cl(nom) = = 25.3a v th(max) = 110mv. therefore, i cl(max) = = = = 51.6a therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3m ? embedded pcb trace is: 14.2a < i cl < 51.6a, with 25.3a being the nominal overload condi- tion. there may be applications whose layout will require the use of two extra filter components, a 510 ? resistor in series with the i sense pin, and a 0.1f capacitor between the i sense and v fb pins. these are needed for proper current limit operation and the resistor value is layout dependent. this series resistor affects the calculation of the current limit setpoint, and has to be taken into account when determining an effective current limit. the calculations below show how the current limit set- point is determined when this 510 ? is taken into consider- ation. v trip = v th + (i sense r isense ) ? (r fb i fb ) where v trip = voltage across the droop resistor that trips the i sense comparator v th = internal i sense comparator threshold i sense = i sense bias current r isense = i sense pin 510 ? filter resistor r fb = v fb pin 3.3k filter resistor i fb = v fb bias current minimum current sense resistor (droop resistor) voltage drop required for current limit when r isense is used v trip(min) = 55mv + (13a 510) ? (3.3k 1a) = 55mv + 6.6mv ? 3.3mv = 58.3mv nominal current sense resistor (droop resistor) voltage drop required for current limit when r isense is used v trip(nom) = 76mv + (30a 510) ? (3.3k 0.1a) = 76mv + 15.3mv ? 0.33mv = 90.97mv maximum current sense resistor (droop resistor) voltage drop required for current limit when r isense is used v trip(max) = 110mv + (50a 510) = 110mv + 25.5mv = 135.5mv the value of r sense (current sense pcb trace) is then calcu- lated: r sense(max) = = 4.1m ? r sense(nom) = = = 3.18m ? the range of load currents that will cause the internal cur- rent sense comparator to detect an overload condition is as follows: nominal current limit setpoint i cl(nom) = v trip(nom) / r sense(nom) therefore, i cl(nom) = 90.97mv / 3.18m ? = 28.6a 4.1m ? m 1.29 r sense(max) 1.29 58.3mv 14.2a 110mv 3m ? 0.7 1 110mv r sense 0.7 1 110mv r sense(min) 76mv 3m ? v th(typ) r sense(nom) 55mv 14.2a v th(min) i cl(min) application information: continued CS5166
CS5166 16 maximum current limit setpoint i cl(max) = v trip(max) / r sense(max) therefore, i cl(max) = 135mv / 3.18m ? 0.71 = 60a therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3m ? embedded pcb trace is: 14.2a < icl 60a, with 28.6a being the nominal overload condition. design rules for using a droop resistor the basic equation for laying an embedded resistor is: r ar = or r = where: a= w t = cross-sectional area = the copper resistivity ( ? - mil) l= length (mils) w = width (mils) t = thickness (mils) for most pcbs the copper thickness, t, is 35m (1.37 mils) for one ounce copper. = 717.86 ? -mil for a pentium ? ii load of 14.2a the resistance needed to create a 43mv drop at full load is: r droop = = = 3.0m ? the resistivity of the copper will drift with the temperature according to the following guidelines: ? r = 12% @ t a = +50 ? c ? r = 34% @t a = +100 ? c droop resistor width calculations the droop resistor must have the ability to handle the load current and therefore requires a minimum width which is calculated as follows (assume one ounce copper thickness): 43mv 14.2a 43mv i out l (w t) l a application information: continued v id1 v id4 v id3 v id2 comp irl3103s 12v 5v 1.2 h gate(h) gate(l) pgnd 1200 f/10v x 3 1 f ss lgnd 330pf 0.1 f v id0 1200 f 10v x 5 CS5166 v fb c off v cc pwrgd i sense 3.0m ? 1000pf 510 3.3k 0.1 f 0.1 f v id1 v id4 v id3 v id2 comp irl3103s 12v 5v 1.2 h gate(h) gate(l) pgnd 1200 f/10v x 3 1 f ss lgnd 330pf v id0 CS5166 v fb c off v cc i sense 3.0m ? 1000pf 510 3.3k 0.1 f 0.1 f v id0 pwrgd v id3 v id4 v id2 v id1 2.8v/30a power supply irl3103s irl3103s figure 23: current sharing of a 2.8v/30a power supply using two CS5166 synchronous buck regulators.
CS5166 17 application information: continued w = where: w = minimum width (in mils) required for proper power dissipation, and i load load current amps. the pentium ? ii maximum load current is 14.2a. therefore: w = = 284 mils = 0.7213cm droop resistor length calculation l = = = 1626 mil = 4.13cm implementing current sharing using the ?droop resistor? in addition to improving load transient performance, the CS5166 v 2 tm control method allows the droop resistor to provide the additional capability to easily implement cur- rent sharing. figure 23 shows a simplified schematic of two current sharing synchronous buck regulators. each buck regulator?s droop resistor is terminated at the load. the pwm control signal from each error amp is con- nected together, causing the inner pwm loop to regulate to a common voltage. since the voltage at each resistor termi- nal is the same, this configuration results in equal voltage being applied across each matched droop resistor. the result is equal current flowing through each buck regula- tor. an additional benefit is that synchronization to a com- mon switching frequency tends to be achieved because each regulator shares a common pwm ramp signal. in practice, each buck regulator will regulate to a slightly different output voltage due to mismatching of the pwm comparators, slope of the pwm ramp (output voltage rip- ple), and propagation delays. at light loads, the result can be very poor current sharing. with zero output current, some regulators may be sourcing current while others may be sinking current. this results in additional power dissipation and lower effi- ciency than would be obtained by a single regulator. this is usually not an issue since efficiency is most important when a supply is fully loaded. this effect is similar to the difference in efficiency between synchronous and non-synchronous buck regulators. synchronous buck regulators have lower efficiency at light loads because inductor current is always continuous, flow- ing from the load to ground during switch off-time through the synchronous rectifier. under full load condi- tions, the synchronous design is more efficient due to the lower voltage drop across the synchronous rectifier. likewise, the efficiency of droop sharing regulators will be lower at light loads due to the continuous current flow in the droop resistors. efficiency at heavy loads tends to be higher due to reduced i 2 r losses. the output current of each regulator can be calculated from: i n = (v out(n) - v out ) / r droop(n) where: v out(n) and r droop(n) are the output voltage and droop resistance of a particular regulator and v out is the system output voltage. output current is the sum of each regulator?s current: i out = i1 + i2 + ? + i n current sharing improves with increasing load current. the increasing voltage drop across the droop resistor due to increasing load current eventually swamps out the dif- ferences in regulator output voltages. if a large enough voltage can be developed across the droop resistors, cur- rent sharing accuracy will be determined solely by their matching. to realize the benefits of current sharing, it is not necessary to obtain perfect matching. keeping output currents within +/- 10% is usually acceptable. for microprocessor applications, the value of the droop resistor must be selected to optimize adaptive voltage positioning, current sharing, current limit and efficiency. current sharing is realized by simply connecting the comp pins of the respective buck regulators, as shown in figure 23. figure 24 shows operation with no load. in this case, there is insufficient output voltage ripple across the droop resis- tors to produce complete synchronization. duty cycle is close to the theoretical 56% (v out /v in ) resulting in a switching frequency of approximately 275khz. figure 25 shows operation with a 30 amp load. synchronization between the two regulators is now obtained due to increased ripple voltage. increased losses cause the v 2 tm control loop to increase on-time to compen- sate. this results in a larger duty cycle and a correspond- ing decrease in switching frequency to 233khz. figure 24: no load waveforms. trace 1 output voltage ripple trace 2 buck regulator #1 inductor switching node trace 3 buck regulator #2 inductor switching node 0.0030 284 1.37 717.86 r droop w t 14.2a 0.05 i load 0.05
figure 25: 30a load waveforms. figure 26: 15a load transient waveforms. figure 26 shows supply response to a 15a load step with a 30a/s slew rate. the v 2 tm control loop immediately forces the duty cycle to 100%, ramping the current in both inductors up. a voltage spike of 136mv due to output capacitor impedance occurs. the inductive component of the spike due to esl recovers within several microseconds. the resistive component due to esr decreases as inductor current replaces capacitor current. the benefit of adaptive voltage positioning in reducing the voltage spike can readily be seen. the differences in dc voltage and duty cycle can also be observed. this particu- lar transient occurred near the beginning of regulator off- time, resulting in a longer recovery time and increased voltage spike. output inductor the inductor should be selected based on its inductance, current capability, and dc resistance. increasing the induc- tor value will decrease output voltage ripple, but degrade transient response. inductor ripple current ripple current = example: v in = +5v, v out = +2.8v, i load = 14.2a, l = 1.2h, freq = 200khz ripple current = = 5.1a output ripple voltage v ripple = inductor ripple current output capacitor esr example: v in = +5v, v out = +2.8v, i load = 14.2a, l = 1.2h, switching frequency = 200khz output ripple voltage = 5.1a output capacitor esr (from manufacturer?s specs) esr of output capacitors to limit output voltage spikes esr = this applies for current spikes that are faster than regula- tor response time. printed circuit board resistance will add to the esr of the output capacitors. in order to limit spikes to 100mv for a 14.2a load step, esr = 0.1/14.2 = 0.007 ? inductor peak current peak current = maximum load current + () example: v in = +5v, v out = +2.8v, i load = 14.2a, l = 1.2h, freq = 200khz peak current = 14.2a + (5.1/2) = 16.75a a key consideration is that the inductor must be able to deliver the peak current at the switching frequency with- out saturating. response time to load increas e (limited by inductor value unless maximum on-time is exceeded) response time = example: v in = +5v, v out = +2.8v, l = 1.2h, 14.2a change in load current response time = = 7.7s 1.2h 14.2a (5v-2.8v) l ? i out (v in -v out ) ripple current 2 ? v out ? i out [(5v-2.8v) 2.8v] [200khz 1.2h 5v] [(v in - v out ) v out ] ( switching frequency l v in ) trace 1 output voltage ripple trace 2 buck regulator #1 inductor switching node trace 3 buck regulator #2 inductor switching node trace 1 output voltage ripple trace 2 buck regulator #1 inductor switching node trace 3 buck regulator #2 inductor switching node application information: continued 18 CS5166
19 response time to load decrease (limited by inductor value) response time = example: v out = +2.8v, 14.2a change in load current, l = 1.2h response time = = 6.1s input and output capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to pro- vide acceptable ripple on the input supply lines and regu- lator output voltage. key specifications for input capacitors are their ripple rating, while esr is important for output capacitors. for best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. thermal considerations for power mosfets and diodes in order to maintain good reliability, the junction tempera- ture of the semiconductor components should be kept to a maximum of 150c or lower. the thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: thermal impedance = a heatsink may be added to to-220 components to reduce their thermal impedance. a number of pc board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. emi management as a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. when designing for compliance with emi/emc regulations, additional components may be added to reduce noise emissions. these components are not required for regulator operation and experimental results may allow them to be eliminated. the input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. placement of the power component to minimize routing distance will also help to reduce emissions. figure 27: filter components. figure 28: input filter. layout guidelines when laying out the cpu buck regulator on a printed cir- cuit board, the following checklist should be used to ensure proper operation of the CS5166. 1) rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2) keep high currents out of sensitive ground connections. avoid connecting the ic gnd (lgnd) between the source of the lower fet and the input capacitor gnd. 3) avoid ground loops as they pick up noise. use star or single point grounding. 4) for high power buck regulators on double-sided pcbs a single large ground plane (usually the bottom) is recom- mended. 5) even though double-sided pcbs are usually sufficient for a good layout, four-layer pcbs are the optimum approach to reducing susceptibility to noise. use the two internal layers as the +5v and gnd planes, the top layer for the power connections and component vias, and the bot- tom layer for the noise sensitive traces. 6) keep the inductor switching node small by placing the output inductor, switching and synchronous fets close together. 7) the fet gate traces to the ic must be as short, straight, and wide as possible. ideally, the ic has to be placed right next to the fets. 8) use fewer, but larger output capacitors, keep the capaci- tors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9) place the switching fet as close to the +5v input capaci- tors as possible. 10) place the output capacitors as close to the load as possible. + 2 h 1200 f x 3/16v 33 ? 1000pf 2 h t j(max) - t a power thermal management 1.2h 14.2a 2.8v l change in i out v out application information: continued CS5166
CS5166 20 1.325 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.875 1.925 1.975 2.025 2.075 dac output voltage setting (v) output error (%) -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 figure 31: percent output error vs dac voltage setting, v cc = 12v, t a = 25 ? c, v id4 = 0. figure 34: percent output error vs. dac output voltage setting v cc = 12v, t a = 25 ? c, v id4 = 1. typical performance characteristics figure 30: gate(h) & gate(l) falltime vs. load capacitance. 200 160 140 120 100 80 60 40 0 180 0 2000 4000 6000 8000 10000 12000 14000 16000 falltime (ns) v cc =12v t a =25c ? load capacitance (pf) 20 figure 33: dac output voltage vs temperature, dac code = 10111, v cc = 12v. 120 100 80 60 40 20 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 junction temperature ( ? c) dac output voltage deviation (%) 0 200 180 160 140 120 100 80 60 40 20 0 0 2000 4000 6000 8000 10000 12000 14000 16000 v cc =12v t a =25c ? risetime (ns) load capacitance (pf) figure 29: gate(l) risetime vs. load capacitance. figure 32: gate(h) risetime vs. load capacitance. 0 2000 4000 6000 8000 10000 12000 14000 16000 200 180 160 140 120 100 80 60 40 20 0 risetime (ns) v cc =12v t a =25c ? load capacitance (pf) 2.125 2.225 2.325 2.425 2.525 2.625 2.725 2.825 2.925 3.025 3.125 3.225 3.325 3.425 3.525 dac output voltage setting (v) output error (%) 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 11) place the v fb filter resistor in series with the v fb pin (pin 16) right at the pin. 12) place the v fb filter capacitor right at the v fb pin (pin 16). 13) the ?droop? resistor (embedded pcb trace) has to be wide enough to carry the full load current. 14) place the v cc bypass capacitor as close as possible to the v cc pin and connect it to the pgnd pin of the ic. connect the pgnd pin directly to the gnd plane. 15) create a subground (local gnd) plane preferably on the pcb top layer and under the ic controller. connect all logic capacitor returns and the lgnd pin of the ic to this plane. connect the subground plane to the main gnd plane using a minimum of four (4) vias. application information: continued
CS5166 21 +5v CS5166 v id0 mbrs120 mbrs120 1 f irl3103s 1.2 h 3.3k 1000pf 1200 f/10v 1200uf/10v 1 f 0.1 f 0.1 f 330pf v cc v ss pwrgd pentium ? ii system v id0 v id1 v id2 v id3 v id4 x5 x3 3m ? lgnd v id4 v id1 v id2 v id3 c off ss comp v gateh v gatel pgnd v fb v cc pwrgd i sense droop resistor (embedded pcb trace) irl3103s 0.1 f 510 mbrs120 figure 35: +5v to +2.8v @ 14.2a for 300 mhz pentium ? ii. additional application circuits
22 package specification d lead count metric english max min max min 16l so wide 10.50 10.10 .413 .398 thermal data 16l so wide r jc typ 23 ? c/w r ja typ 105 ? c/w package dimensions in mm (inches) package thermal data CS5166 ordering information part number description CS5166gdw16 16l so wide CS5166gdwr16 16l so wide (tape & reel) rev. 6/28/99 ? 1999 cherry semiconductor corporation cherry semiconductor corporation reserves the right to make changes to the specifications without notice. please contact cherry semiconductor corporation for the latest available information. surface mount wide body (dw); 300 mil wide 1.27 (.050) bsc 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) d 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) ref: jedec ms-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004)

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